1. Field of the Invention
The present invention relates to an access frequency estimation apparatus and an access frequency estimation method and, for example, to an apparatus and a method for estimating a frequency of access to a semiconductor storage device for each predetermined region.
2. Description of the Related Art
A high voltage is applied to each of memory cells of a flash memory at an insulating film constituting the memory cell when data is written to the memory cell. An accumulation of application of the high voltage deteriorates the characteristics of the insulating film. An accumulation of deterioration of the characteristics of the insulating film lowers reliability of the memory cell in retaining data. Accordingly, each memory cell has an upper limit of the number of rewritable times.
If writing is concentrated at a certain memory cell, the count of writing data to this memory cell reaches the upper limit earlier than the other memory cells. As a result, reliability of data retention of the whole flash memory is lowered. In order to avoid such a situation, it is desirable that the count of writing data to the memory cells be as even as possible in the entire memory cells.
In order to meet such requirements, most of controllers for controlling a flash memory try to level the count of writing as much as possible in all the memory cells wear leveling).
A flash memory controller for controlling a flash memory is gencrally composed of hardware for controlling a bus of the flash memory and software for controlling an operation of the hardware. The software performs the wear leveling.
It is necessary to verify whether the software of the flash memory controller performs appropriate wear leveling at the designing stage of the flash memory controller. As the verification methods, the following two methods are so far possible.
A first method involves visual verification of a flowchart representing an operation of the software, and confirming whether the hardware operates in accordance with the flowchart by means of a simulator or the like. The first method does not verify an actual operation of the flash memory controller upon a write operation. As a result, the method cannot find a defect in wear leveling resulting from an unpredictable problem that cannot be found by the flowchart and simulation. Furthermore, the method includes confirmation performed by a human being, resulting in possible mistakes.
A second method involves actual verification of signals on a bus of the flash memory manufactured on an experimental basis. A general-purpose measuring instrument such as a logic analyzer is used because a protocol analyzer exclusively used for a flash memory to detect a command or the like peculiar to the flash memory is not commercially available so far. A logic analyzer outputs signals on the bus, which is an object to be verified, at appropriate intervals, and numerating the signals, for example, on an image along the time base. However, as described above, since the general-purpose logic analyzer cannot recognize a command peculiar to the flash memory, and thus it takes in the state (for example, “0” or “1”) of each signal at each point of time. Further, it is necessary to extract write commands and write addresses from the acquired data to analyze the write commands and the write addresses. Thus, the data to be taken in and stored and the resulting throughput are enormous. Accordingly, it is impossible to actually carry out the second method.
Jpn. Pat. Appln. KOKAI Publication No. 6-52694 discloses monitoring signals transferred to or from a flash memory from or to a memory controller, and measuring a period of time from a data erasure command, with data erasure completion or incompletion, to data erasure completion.